1. Field of the Invention
The invention relates to a method of testing the contents of a read-only memory in an integrated circuit which also comprises a processor which is controlled by the contents of the read-only memory and also comprises an arithmetic unit and a storage register. The processor is connected to external connections of the integrated circuit and is switchable to a test mode in which the contents of the read-only memory in the integrated circuit are compared with externally supplied test data, an error message is generated in the case of non-correspondence. The invention also relates to a device for performing the method.
2. Prior Art
A method of this kind and an appropriate device are known from U.S. Pat. No. 4,777,586. The program stored in the read-only memory is often developed by the customer at substantial expense, possibly with the assistance of the manufacturer of the microcontroller, so that this program represents a substantial value. In order to ensure that a third party cannot acquire such a microcontroller and read the contents of the read-only memory in order to build or program microcontrollers so that said third party would save the expenditure for the development of the program, testing of the contents of the read-only memory must be possible without these contents being directly detectable from the outside.
In accordance with said U.S. Pat. No. 4,777,586 this is realized in that the contents of the read-only memory are read by means of a separately generated clock signal in order to be applied to a separate comparator which receives externally applied test data upon inversion of said clock signal. The occurrence of errors is stored and output to the environment, via a separate output, after a predetermined number of test steps. A separate counter is required for counting-this number of test steps. The comparator is provided with registers for the intermediate storage of the data read from the read-only memory and the test data. Thus, a number of additional elements are required for testing the contents of the read-only memory, which elements require an additional surface area on the integrated circuit.